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  4.     <title>Memory simulation in &mu;Csim</title>
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  7.     <h1>Memory simulation in <i>&mu;Csim</i></h1>
  8.     Typical microprocessor system can look like this:
  9.     <p><img src="cpu-mem.svg" alt="[CPU-memory connection]" border="0"></p>
  10.     <h3><a name="address_space">Address space</a></h3>
  11.     In our terminology "<b>address space</b>" means a set of:
  12.     <ul>
  13.       <li>address bus lines </li>
  14.       <li>data bus lines </li>
  15.       <li>control (read/write) lines</li>
  16.     </ul>
  17.     Bus lines can be shared by address spaces, in this case number of control
  18.     line sets specifies the address spaces.
  19.     <p>Microcontrollers usually have more address spaces. Some is used inside
  20.       only, some can be used for external memories. </p>
  21.     <p>Address space does not store any value. It just specifies range of
  22.       addresses by <i>start address</i> (which is not necessarily zero) and <i>size</i>
  23.       which the CPU can provide when it tries to access a memory location.</p>
  24.     <h3><a name="chip">Memory chip</a></h3>
  25.     "<b>Memory chip</b>" is a circuit which can hold values in cells. Cells are
  26.     indexed from 0 up to size-1. Each cell stores some (usually 8) bits.
  27.     <p><img src="chip.svg" alt="[Memory chip]" border="0"></p>
  28.     <h3><a name="address_decoder">Address decoder</a></h3>
  29.     Addresses coming from an address space via address bus must be routed to
  30.     memory and translated to cell indexes. This is done by the "<b>address
  31.      decoder</b>". It listens addresses on the bus and control lines and
  32.     enables exactly one memory chip. This way cells of the memory chip appear in
  33.     the address space.
  34.     <p><img src="decoded.svg" boder="0" alt="[Decoded addresses]"> </p>
  35.     <p>It is possible that some addresses are not decoded. Writing to such an
  36.       address results data to be lost. Reading of a non-decoded address results
  37.       random value. Pullup or pulldown resistors can be applied to data bus
  38.       lines to provide a specific value for read operations. </p>
  39.     <p>As it shown above, it is also possible that some cells of a chip is not
  40.       mapped to any address. </p>
  41.     <h3><a name="shared_chips">Mixed address spaces (shared chips)</a></h3>
  42.     Decoder connects an address of an address space to a cell of a memory chip.
  43.     Only one cell can be connected to each addresses but same cell can be
  44.     connected to more than one address spaces. This is done by routing different
  45.     control lines to the same chip through logic <b>L</b>:
  46.     <p><img src="share-chip.svg" alt="[Sharing memchip]" border="0"> </p>
  47.     <p>Because each cell of a memory chip uses same read/write control, in real
  48.       world it is not possible to share individual cells of a chip between
  49.       address spaces. In &mu;Csim simulator we can define as many address decoders
  50.       as we want so it is possible to map any cell to any address. </p>
  51.     <h3><a name="banking">Memory banking</a></h3>
  52.     <p>Banking...</p>
  53.     <h3><a name="banding">Bit banding</a></h3>
  54.     <p>Banding...</p>
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