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  1. /**
  2.   ******************************************************************************
  3.   * @file    opora_ext_bus_cntrl_defs.h
  4.   * @author  Phyton Application Team
  5.   * @version V1.0.0
  6.   * @date
  7.   * @brief   This file contains all the Special Function Registers definitions
  8.   *          for the EXT_BUS_CNTRL peripheral unit used in the Milandr OPORA
  9.   *          microcontrollers.
  10.   ******************************************************************************
  11.   * @copy
  12.   *
  13.   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  14.   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  15.   * TIME. AS A RESULT, PHYTON SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
  16.   * OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  17.   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  18.   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  19.   *
  20.   * <h2><center>&copy; COPYRIGHT 2010 Phyton</center></h2>
  21.   ******************************************************************************
  22.   * FILE opora_ext_bus_cntrl_defs.h
  23.   */
  24.  
  25. /* Define to prevent recursive inclusion -------------------------------------*/
  26. #ifndef __OPORA_EXT_BUS_CNTRL_DEFS_H
  27. #define __OPORA_EXT_BUS_CNTRL_DEFS_H
  28.  
  29. /** @addtogroup __CMSIS CMSIS
  30.   * @{
  31.   */
  32.  
  33. /** @addtogroup __OPORA_Peripheral_Units OPORA Peripheral Units
  34.   * @{
  35.   */
  36.  
  37. /** @defgroup Periph_EXT_BUS_CNTRL EXT_BUS_CNTRL
  38.   * @{
  39.   */
  40.  
  41. /** @defgroup Periph_EXT_BUS_CNTRL_Data_Structures Data Structures
  42.   * @{
  43.   */
  44.  
  45. /** @defgroup Periph_EXT_BUS_CNTRL_TypeDef EXT_BUS_CNTRL_TypeDef
  46.   * @{
  47.   */
  48.  
  49. typedef struct {
  50.        uint32_t RESERVED0[20];
  51.   __IO uint32_t NAND_CYCLES;
  52.   __IO uint32_t EXT_BUS_CONTROL;
  53.   __IO uint32_t RAM_CYCLES1;
  54.   __IO uint32_t RAM_CYCLES2;
  55.   __IO uint32_t RAM_CYCLES3;
  56.   __IO uint32_t RAM_CYCLES4;   
  57. } EXT_BUS_CNTRL_TypeDef;
  58.  
  59. /** @} */ /* End of group Periph_EXT_BUS_CNTRL_TypeDef */
  60.  
  61. /** @} */ /* End of group Periph_EXT_BUS_CNTRL_Data_Structures */
  62.  
  63. /** @defgroup Periph_EXT_BUS_CNTRL_Defines Defines
  64.   * @{
  65.   */
  66.  
  67. /** @defgroup Periph_EXT_BUS_CNTRL_EXT_BUS_CNTRL_NAND_CYCLES_Bits EXT_BUS_CNTRL_NAND_CYCLES
  68.   * @{
  69.   */
  70.  
  71. #define EXT_BUS_CNTRL_NAND_CYCLES_t_rc_OFFS     0
  72. #define EXT_BUS_CNTRL_NAND_CYCLES_t_rc_MASK     ((uint32_t)0x0000000F)
  73.  
  74. #define EXT_BUS_CNTRL_NAND_CYCLES_t_wc_OFFS     4
  75. #define EXT_BUS_CNTRL_NAND_CYCLES_t_wc_MASK     ((uint32_t)0x000000F0)
  76.  
  77. #define EXT_BUS_CNTRL_NAND_CYCLES_t_rea_OFFS    8
  78. #define EXT_BUS_CNTRL_NAND_CYCLES_t_rea_MASK    ((uint32_t)0x00000F00)
  79.  
  80. #define EXT_BUS_CNTRL_NAND_CYCLES_t_wp_OFFS     12
  81. #define EXT_BUS_CNTRL_NAND_CYCLES_t_wp_MASK     ((uint32_t)0x0000F000)
  82.  
  83. #define EXT_BUS_CNTRL_NAND_CYCLES_t_whr_OFFS    16
  84. #define EXT_BUS_CNTRL_NAND_CYCLES_t_whr_MASK    ((uint32_t)0x000F0000)
  85.  
  86. #define EXT_BUS_CNTRL_NAND_CYCLES_t_alea_OFFS   20
  87. #define EXT_BUS_CNTRL_NAND_CYCLES_t_alea_MASK   ((uint32_t)0x00F00000)
  88.  
  89. #define EXT_BUS_CNTRL_NAND_CYCLES_t_rr_OFFS     24
  90. #define EXT_BUS_CNTRL_NAND_CYCLES_t_rr_MASK     ((uint32_t)0x0F000000)
  91.  
  92.  
  93. /** @} */ /* End of group Periph_EXT_BUS_CNTRL_EXT_BUS_CNTRL_NAND_CYCLES_Bits */
  94.  
  95. /** @} */ /* End of group Periph_EXT_BUS_CNTRL_Defines */
  96.  
  97. /** @defgroup Periph_EXT_BUS_CNTRL_Defines Defines
  98.   * @{
  99.   */
  100.  
  101. /** @defgroup Periph_EXT_BUS_CNTRL_EXT_BUS_CNTRL_EXT_BUS_CONTROL_Bits EXT_BUS_CNTRL_EXT_BUS_CONTROL
  102.   * @{
  103.   */
  104.  
  105. #define EXT_BUS_CNTRL_EXT_BUS_CONTROL_ROM_OFFS  0
  106. #define EXT_BUS_CNTRL_EXT_BUS_CONTROL_ROM       ((uint32_t)0x00000001)
  107.  
  108. #define EXT_BUS_CNTRL_EXT_BUS_CONTROL_RAM_OFFS  1
  109. #define EXT_BUS_CNTRL_EXT_BUS_CONTROL_RAM       ((uint32_t)0x00000002)
  110.  
  111. #define EXT_BUS_CNTRL_EXT_BUS_CONTROL_NAND_OFFS 2
  112. #define EXT_BUS_CNTRL_EXT_BUS_CONTROL_NAND      ((uint32_t)0x00000004)
  113.  
  114. #define EXT_BUS_CNTRL_EXT_BUS_CONTROL_CPOL_OFFS 3
  115. #define EXT_BUS_CNTRL_EXT_BUS_CONTROL_CPOL      ((uint32_t)0x00000008)
  116.  
  117. #define EXT_BUS_CNTRL_EXT_BUS_CONTROL_BUSY_OFFS 7
  118. #define EXT_BUS_CNTRL_EXT_BUS_CONTROL_BUSY      ((uint32_t)0x00000080)
  119.  
  120. #define EXT_BUS_CNTRL_EXT_BUS_CONTROL_WAIT_STATE_OFFS 12
  121. #define EXT_BUS_CNTRL_EXT_BUS_CONTROL_WAIT_STATE_MASK ((uint32_t)0x0000F000)
  122.  
  123.  
  124. /** @} */ /* End of group Periph_EXT_BUS_CNTRL_EXT_BUS_CNTRL_EXT_BUS_CONTROL_Bits */
  125.  
  126. /** @} */ /* End of group Periph_EXT_BUS_CNTRL_Defines */
  127.  
  128. /** @} */ /* End of group Periph_EXT_BUS_CNTRL */
  129.  
  130. /** @} */ /* End of group __OPORA_Peripheral_Units */
  131.  
  132. /** @} */ /* End of group __CMSIS */
  133.  
  134. #endif /* __OPORA_EXT_BUS_CNTRL_DEFS_H */
  135.  
  136. /******************* (C) COPYRIGHT 2010 Phyton *********************************
  137. *
  138. * END OF FILE opora_ext_bus_cntrl_defs.h */
  139.