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  1. /**
  2.   ******************************************************************************
  3.   * @file    opora_rst_clk_defs.h
  4.   * @author  Phyton Application Team
  5.   * @version V1.0.0
  6.   * @date
  7.   * @brief   This file contains all the Special Function Registers definitions
  8.   *          for the RST_CLK peripheral unit used in the Milandr OPORA
  9.   *          microcontrollers.
  10.   ******************************************************************************
  11.   * @copy
  12.   *
  13.   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  14.   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  15.   * TIME. AS A RESULT, PHYTON SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
  16.   * OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  17.   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  18.   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  19.   *
  20.   * <h2><center>&copy; COPYRIGHT 2010 Phyton</center></h2>
  21.   ******************************************************************************
  22.   * FILE opora_rst_clk_defs.h
  23.   */
  24.  
  25. /* Define to prevent recursive inclusion -------------------------------------*/
  26. #ifndef __OPORA_RST_CLK_DEFS_H
  27. #define __OPORA_RST_CLK_DEFS_H
  28.  
  29. /** @addtogroup __CMSIS CMSIS
  30.   * @{
  31.   */
  32.  
  33. /** @addtogroup __OPORA_Peripheral_Units OPORA Peripheral Units
  34.   * @{
  35.   */
  36.  
  37. /** @defgroup Periph_RST_CLK RST_CLK
  38.   * @{
  39.   */
  40.  
  41. /** @defgroup Periph_RST_CLK_Data_Structures Data Structures
  42.   * @{
  43.   */
  44.  
  45. /** @defgroup Periph_RST_CLK_TypeDef RST_CLK_TypeDef
  46.   * @{
  47.   */
  48.  
  49. typedef struct {
  50.   __IO uint32_t CLOCK_STATUS;
  51.   __IO uint32_t PLL_CONTROL;
  52.   __IO uint32_t HS_CONTROL;
  53.   __IO uint32_t CPU_CLOCK;
  54.   __IO uint32_t USB_CLOCK;
  55.   __IO uint32_t ADC_MCO_CLOCK;
  56.   __IO uint32_t RTC_CLOCK;
  57.   __IO uint32_t PER_CLOCK;
  58.   __IO uint32_t CAN_CLOCK;
  59.   __IO uint32_t TIM_CLOCK;
  60.   __IO uint32_t UART_CLOCK;
  61.   __IO uint32_t SSP_CLOCK;
  62.        uint32_t RESERVED;
  63.   __IO uint32_t ETH_CLOCK;
  64. } RST_CLK_TypeDef;
  65.  
  66. /** @} */ /* End of group Periph_RST_CLK_TypeDef */
  67.  
  68. /** @} */ /* End of group Periph_RST_CLK_Data_Structures */
  69.  
  70. /** @defgroup Periph_RST_CLK_Defines Defines
  71.   * @{
  72.   */
  73.  
  74. /** @defgroup Periph_RST_CLK_RST_CLK_CLOCK_STATUS_Bits RST_CLK_CLOCK_STATUS
  75.   * @{
  76.   */
  77.  
  78. #define RST_CLK_CLOCK_STATUS_PLL_USB_RDY_OFFS   0
  79. #define RST_CLK_CLOCK_STATUS_PLL_USB_RDY        ((uint32_t)0x00000001)
  80.  
  81. #define RST_CLK_CLOCK_STATUS_PLL_CPU_RDY_OFFS   1
  82. #define RST_CLK_CLOCK_STATUS_PLL_CPU_RDY        ((uint32_t)0x00000002)
  83.  
  84. #define RST_CLK_CLOCK_STATUS_HSE_RDY_OFFS       2
  85. #define RST_CLK_CLOCK_STATUS_HSE_RDY            ((uint32_t)0x00000004)
  86.  
  87.  
  88. /** @} */ /* End of group Periph_RST_CLK_RST_CLK_CLOCK_STATUS_Bits */
  89.  
  90. /** @} */ /* End of group Periph_RST_CLK_Defines */
  91.  
  92. /** @defgroup Periph_RST_CLK_Defines Defines
  93.   * @{
  94.   */
  95.  
  96. /** @defgroup Periph_RST_CLK_RST_CLK_PLL_CONTROL_Bits RST_CLK_PLL_CONTROL
  97.   * @{
  98.   */
  99.  
  100. #define RST_CLK_PLL_CONTROL_PLL_USB_ON_OFFS     0
  101. #define RST_CLK_PLL_CONTROL_PLL_USB_ON          ((uint32_t)0x00000001)
  102.  
  103. #define RST_CLK_PLL_CONTROL_PLL_USB_RLD_OFFS    1
  104. #define RST_CLK_PLL_CONTROL_PLL_USB_RLD         ((uint32_t)0x00000002)
  105.  
  106. #define RST_CLK_PLL_CONTROL_PLL_CPU_ON_OFFS     2
  107. #define RST_CLK_PLL_CONTROL_PLL_CPU_ON          ((uint32_t)0x00000004)
  108.  
  109. #define RST_CLK_PLL_CONTROL_PLL_CPU_PLD_OFFS    3
  110. #define RST_CLK_PLL_CONTROL_PLL_CPU_PLD         ((uint32_t)0x00000008)
  111.  
  112. #define RST_CLK_PLL_CONTROL_PLL_USB_MUL_OFFS    4
  113. #define RST_CLK_PLL_CONTROL_PLL_USB_MUL_MASK    ((uint32_t)0x000000F0)
  114.  
  115. #define RST_CLK_PLL_CONTROL_PLL_CPU_MUL_OFFS    8
  116. #define RST_CLK_PLL_CONTROL_PLL_CPU_MUL_MASK    ((uint32_t)0x00000F00)
  117.  
  118. #define RST_CLK_PLL_CONTROL_PLL_CPU_MUL_2               ((uint32_t)0x00000100)
  119. #define RST_CLK_PLL_CONTROL_PLL_CPU_MUL_3               ((uint32_t)0x00000200)
  120. #define RST_CLK_PLL_CONTROL_PLL_CPU_MUL_4               ((uint32_t)0x00000300)
  121. #define RST_CLK_PLL_CONTROL_PLL_CPU_MUL_5               ((uint32_t)0x00000400)
  122. #define RST_CLK_PLL_CONTROL_PLL_CPU_MUL_6               ((uint32_t)0x00000500)
  123. #define RST_CLK_PLL_CONTROL_PLL_CPU_MUL_7               ((uint32_t)0x00000600)
  124. #define RST_CLK_PLL_CONTROL_PLL_CPU_MUL_8               ((uint32_t)0x00000700)
  125. #define RST_CLK_PLL_CONTROL_PLL_CPU_MUL_9               ((uint32_t)0x00000800)
  126. #define RST_CLK_PLL_CONTROL_PLL_CPU_MUL_10              ((uint32_t)0x00000900)
  127. #define RST_CLK_PLL_CONTROL_PLL_CPU_MUL_11              ((uint32_t)0x00000A00)
  128. #define RST_CLK_PLL_CONTROL_PLL_CPU_MUL_12              ((uint32_t)0x00000B00)
  129. #define RST_CLK_PLL_CONTROL_PLL_CPU_MUL_13              ((uint32_t)0x00000C00)
  130. #define RST_CLK_PLL_CONTROL_PLL_CPU_MUL_14              ((uint32_t)0x00000D00)
  131. #define RST_CLK_PLL_CONTROL_PLL_CPU_MUL_15              ((uint32_t)0x00000E00)
  132. #define RST_CLK_PLL_CONTROL_PLL_CPU_MUL_16              ((uint32_t)0x00000F00)
  133.  
  134. /** @} */ /* End of group Periph_RST_CLK_RST_CLK_PLL_CONTROL_Bits */
  135.  
  136. /** @} */ /* End of group Periph_RST_CLK_Defines */
  137.  
  138. /** @defgroup Periph_RST_CLK_Defines Defines
  139.   * @{
  140.   */
  141.  
  142. /** @defgroup Periph_RST_CLK_RST_CLK_HS_CONTROL_Bits RST_CLK_HS_CONTROL
  143.   * @{
  144.   */
  145.  
  146. #define RST_CLK_HS_CONTROL_HSE_ON_OFFS          0
  147. #define RST_CLK_HS_CONTROL_HSE_ON               ((uint32_t)0x00000001)
  148.  
  149. #define RST_CLK_HS_CONTROL_HSE_BYP_OFFS         1
  150. #define RST_CLK_HS_CONTROL_HSE_BYP              ((uint32_t)0x00000002)
  151.  
  152.  
  153. /** @} */ /* End of group Periph_RST_CLK_RST_CLK_HS_CONTROL_Bits */
  154.  
  155. /** @} */ /* End of group Periph_RST_CLK_Defines */
  156.  
  157. /** @defgroup Periph_RST_CLK_Defines Defines
  158.   * @{
  159.   */
  160.  
  161. /** @defgroup Periph_RST_CLK_RST_CLK_CPU_CLOCK_Bits RST_CLK_CPU_CLOCK
  162.   * @{
  163.   */
  164.  
  165. #define RST_CLK_CPU_CLOCK_CPU_C1_SEL_OFFS       0
  166. #define RST_CLK_CPU_CLOCK_CPU_C1_SEL_MASK       ((uint32_t)0x00000003)
  167.  
  168. #define RST_CLK_CPU_CLOCK_CPU_C2_SEL_OFFS       2
  169. #define RST_CLK_CPU_CLOCK_CPU_C2_SEL            ((uint32_t)0x00000004)
  170.  
  171. #define RST_CLK_CPU_CLOCK_CPU_C3_SEL_OFFS       4
  172. #define RST_CLK_CPU_CLOCK_CPU_C3_SEL_MASK       ((uint32_t)0x000000F0)
  173.  
  174. #define RST_CLK_CPU_CLOCK_HCLK_SEL_OFFS         8
  175. #define RST_CLK_CPU_CLOCK_HCLK_SEL_MASK         ((uint32_t)0x00000300)
  176.  
  177.  
  178. /** @} */ /* End of group Periph_RST_CLK_RST_CLK_CPU_CLOCK_Bits */
  179.  
  180. /** @} */ /* End of group Periph_RST_CLK_Defines */
  181.  
  182. /** @defgroup Periph_RST_CLK_Defines Defines
  183.   * @{
  184.   */
  185.  
  186. /** @defgroup Periph_RST_CLK_RST_CLK_USB_CLOCK_Bits RST_CLK_USB_CLOCK
  187.   * @{
  188.   */
  189.  
  190. #define RST_CLK_USB_CLOCK_USB_C1_SEL_OFFS       0
  191. #define RST_CLK_USB_CLOCK_USB_C1_SEL_MASK       ((uint32_t)0x00000003)
  192.  
  193. #define RST_CLK_USB_CLOCK_USB_C2_SEL_OFFS       2
  194. #define RST_CLK_USB_CLOCK_USB_C2_SEL            ((uint32_t)0x00000004)
  195.  
  196. #define RST_CLK_USB_CLOCK_CPU_C3_SEL_OFFS       4
  197. #define RST_CLK_USB_CLOCK_CPU_C3_SEL_MASK       ((uint32_t)0x000000F0)
  198.  
  199. #define RST_CLK_USB_CLOCK_USB_CL_KEN_OFFS       8
  200. #define RST_CLK_USB_CLOCK_USB_CL_KEN            ((uint32_t)0x00000100)
  201.  
  202.  
  203. /** @} */ /* End of group Periph_RST_CLK_RST_CLK_USB_CLOCK_Bits */
  204.  
  205. /** @} */ /* End of group Periph_RST_CLK_Defines */
  206.  
  207. /** @defgroup Periph_RST_CLK_Defines Defines
  208.   * @{
  209.   */
  210.  
  211. /** @defgroup Periph_RST_CLK_RST_CLK_ADC_MCO_CLOCK_Bits RST_CLK_ADC_MCO_CLOCK
  212.   * @{
  213.   */
  214.  
  215. #define RST_CLK_ADC_MCO_CLOCK_ADC_C1_SEL_OFFS   0
  216. #define RST_CLK_ADC_MCO_CLOCK_ADC_C1_SEL_MASK   ((uint32_t)0x00000003)
  217.  
  218. #define RST_CLK_ADC_MCO_CLOCK_ADC_C2_SEL_OFFS   4
  219. #define RST_CLK_ADC_MCO_CLOCK_ADC_C2_SEL_MASK   ((uint32_t)0x00000030)
  220.  
  221. #define RST_CLK_ADC_MCO_CLOCK_ADC_C3_SEL_OFFS   8
  222. #define RST_CLK_ADC_MCO_CLOCK_ADC_C3_SEL_MASK   ((uint32_t)0x00000F00)
  223.  
  224. #define RST_CLK_ADC_MCO_CLOCK_MCO_EN_OFFS       12
  225. #define RST_CLK_ADC_MCO_CLOCK_MCO_EN            ((uint32_t)0x00001000)
  226.  
  227. #define RST_CLK_ADC_MCO_CLOCK_ADC_CLK_EN_OFFS   13
  228. #define RST_CLK_ADC_MCO_CLOCK_ADC_CLK_EN        ((uint32_t)0x00002000)
  229.  
  230.  
  231. /** @} */ /* End of group Periph_RST_CLK_RST_CLK_ADC_MCO_CLOCK_Bits */
  232.  
  233. /** @} */ /* End of group Periph_RST_CLK_Defines */
  234.  
  235. /** @defgroup Periph_RST_CLK_Defines Defines
  236.   * @{
  237.   */
  238.  
  239. /** @defgroup Periph_RST_CLK_RST_CLK_RTC_CLOCK_Bits RST_CLK_RTC_CLOCK
  240.   * @{
  241.   */
  242.  
  243. #define RST_CLK_RTC_CLOCK_HSE_SEL_OFFS          0
  244. #define RST_CLK_RTC_CLOCK_HSE_SEL_MASK          ((uint32_t)0x0000000F)
  245.  
  246. #define RST_CLK_RTC_CLOCK_HSI_SEL_OFFS          4
  247. #define RST_CLK_RTC_CLOCK_HSI_SEL_MASK          ((uint32_t)0x000000F0)
  248.  
  249. #define RST_CLK_RTC_CLOCK_HSE_RTC_EN_OFFS       8
  250. #define RST_CLK_RTC_CLOCK_HSE_RTC_EN            ((uint32_t)0x00000100)
  251.  
  252. #define RST_CLK_RTC_CLOCK_HSI_RTC_EN_OFFS       9
  253. #define RST_CLK_RTC_CLOCK_HSI_RTC_EN            ((uint32_t)0x00000200)
  254.  
  255.  
  256. /** @} */ /* End of group Periph_RST_CLK_RST_CLK_RTC_CLOCK_Bits */
  257.  
  258. /** @} */ /* End of group Periph_RST_CLK_Defines */
  259.  
  260. /** @defgroup Periph_RST_CLK_Defines Defines
  261.   * @{
  262.   */
  263.  
  264. /** @defgroup Periph_RST_CLK_RST_CLK_CAN_CLOCK_Bits RST_CLK_CAN_CLOCK
  265.   * @{
  266.   */
  267.  
  268. #define RST_CLK_CAN_CLOCK_CAN1_BRG_OFFS         0
  269. #define RST_CLK_CAN_CLOCK_CAN1_BRG_MASK         ((uint32_t)0x000000FF)
  270.  
  271. #define RST_CLK_CAN_CLOCK_CAN2_BRG_OFFS         8
  272. #define RST_CLK_CAN_CLOCK_CAN2_BRG_MASK         ((uint32_t)0x0000FF00)
  273.  
  274. #define RST_CLK_CAN_CLOCK_CAN1_CLK_EN_OFFS      24
  275. #define RST_CLK_CAN_CLOCK_CAN1_CLK_EN           ((uint32_t)0x01000000)
  276.  
  277. #define RST_CLK_CAN_CLOCK_CAN2_CLK_EN_OFFS      25
  278. #define RST_CLK_CAN_CLOCK_CAN2_CLK_EN           ((uint32_t)0x02000000)
  279.  
  280.  
  281. /** @} */ /* End of group Periph_RST_CLK_RST_CLK_CAN_CLOCK_Bits */
  282.  
  283. /** @} */ /* End of group Periph_RST_CLK_Defines */
  284.  
  285. /** @defgroup Periph_RST_CLK_Defines Defines
  286.   * @{
  287.   */
  288.  
  289. /** @defgroup Periph_RST_CLK_RST_CLK_TIM_CLOCK_Bits RST_CLK_TIM_CLOCK
  290.   * @{
  291.   */
  292.  
  293. #define RST_CLK_TIM_CLOCK_TIM1_BRG_OFFS         0
  294. #define RST_CLK_TIM_CLOCK_TIM1_BRG_MASK         ((uint32_t)0x000000FF)
  295.  
  296. #define RST_CLK_TIM_CLOCK_TIM2_BRG_OFFS         8
  297. #define RST_CLK_TIM_CLOCK_TIM2_BRG_MASK         ((uint32_t)0x0000FF00)
  298.  
  299. #define RST_CLK_TIM_CLOCK_TIM3_BRG_OFFS         16
  300. #define RST_CLK_TIM_CLOCK_TIM3_BRG_MASK         ((uint32_t)0x00FF0000)
  301.  
  302. #define RST_CLK_TIM_CLOCK_TIM1_CLK_EN_OFFS      24
  303. #define RST_CLK_TIM_CLOCK_TIM1_CLK_EN           ((uint32_t)0x01000000)
  304.  
  305. #define RST_CLK_TIM_CLOCK_TIM2_CLK_EN_OFFS      25
  306. #define RST_CLK_TIM_CLOCK_TIM2_CLK_EN           ((uint32_t)0x02000000)
  307.  
  308. #define RST_CLK_TIM_CLOCK_TIM3_CLK_EN_OFFS      26
  309. #define RST_CLK_TIM_CLOCK_TIM3_CLK_EN           ((uint32_t)0x04000000)
  310.  
  311.  
  312. /** @} */ /* End of group Periph_RST_CLK_RST_CLK_TIM_CLOCK_Bits */
  313.  
  314. /** @} */ /* End of group Periph_RST_CLK_Defines */
  315.  
  316. /** @defgroup Periph_RST_CLK_Defines Defines
  317.   * @{
  318.   */
  319.  
  320. /** @defgroup Periph_RST_CLK_RST_CLK_UART_CLOCK_Bits RST_CLK_UART_CLOCK
  321.   * @{
  322.   */
  323.  
  324. #define RST_CLK_UART_CLOCK_UART1_BRG_OFFS       0
  325. #define RST_CLK_UART_CLOCK_UART1_BRG_MASK       ((uint32_t)0x000000FF)
  326.  
  327. #define RST_CLK_UART_CLOCK_UART2_BRG_OFFS       8
  328. #define RST_CLK_UART_CLOCK_UART2_BRG_MASK       ((uint32_t)0x0000FF00)
  329.  
  330. #define RST_CLK_UART_CLOCK_UART1_CLK_EN_OFFS    24
  331. #define RST_CLK_UART_CLOCK_UART1_CLK_EN         ((uint32_t)0x01000000)
  332.  
  333. #define RST_CLK_UART_CLOCK_UART2_CLK_EN_OFFS    25
  334. #define RST_CLK_UART_CLOCK_UART2_CLK_EN         ((uint32_t)0x02000000)
  335.  
  336.  
  337. /** @} */ /* End of group Periph_RST_CLK_RST_CLK_UART_CLOCK_Bits */
  338.  
  339. /** @} */ /* End of group Periph_RST_CLK_Defines */
  340.  
  341. /** @defgroup Periph_RST_CLK_Defines Defines
  342.   * @{
  343.   */
  344.  
  345. /** @defgroup Periph_RST_CLK_RST_CLK_SSP_CLOCK_Bits RST_CLK_SSP_CLOCK
  346.   * @{
  347.   */
  348.  
  349. #define RST_CLK_SSP_CLOCK_SSP1_BRG_OFFS         0
  350. #define RST_CLK_SSP_CLOCK_SSP1_BRG_MASK         ((uint32_t)0x000000FF)
  351.  
  352. #define RST_CLK_SSP_CLOCK_SSP2_BRG_OFFS         8
  353. #define RST_CLK_SSP_CLOCK_SSP2_BRG_MASK         ((uint32_t)0x0000FF00)
  354.  
  355. #define RST_CLK_SSP_CLOCK_SSP1_CLK_EN_OFFS      24
  356. #define RST_CLK_SSP_CLOCK_SSP1_CLK_EN           ((uint32_t)0x01000000)
  357.  
  358. #define RST_CLK_SSP_CLOCK_SSP2_CLK_EN_OFFS      25
  359. #define RST_CLK_SSP_CLOCK_SSP2_CLK_EN           ((uint32_t)0x02000000)
  360.  
  361.  
  362. /** @} */ /* End of group Periph_RST_CLK_RST_CLK_SSP_CLOCK_Bits */
  363.  
  364. /** @} */ /* End of group Periph_RST_CLK_Defines */
  365.  
  366. /** @} */ /* End of group Periph_RST_CLK */
  367.  
  368. /** @} */ /* End of group __OPORA_Peripheral_Units */
  369.  
  370. /** @} */ /* End of group __CMSIS */
  371.  
  372. #endif /* __OPORA_RST_CLK_DEFS_H */
  373.  
  374. /******************* (C) COPYRIGHT 2010 Phyton *********************************
  375. *
  376. * END OF FILE opora_rst_clk_defs.h */
  377.