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  1. /**
  2.   ******************************************************************************
  3.   * @file    opora_timer_defs.h
  4.   * @author  Phyton Application Team
  5.   * @version V1.0.0
  6.   * @date
  7.   * @brief   This file contains all the Special Function Registers definitions
  8.   *          for the TIMER peripheral unit used in the Milandr OPORA
  9.   *          microcontrollers.
  10.   ******************************************************************************
  11.   * @copy
  12.   *
  13.   * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  14.   * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  15.   * TIME. AS A RESULT, PHYTON SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
  16.   * OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  17.   * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  18.   * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  19.   *
  20.   * <h2><center>&copy; COPYRIGHT 2010 Phyton</center></h2>
  21.   ******************************************************************************
  22.   * FILE opora_timer_defs.h
  23.   */
  24.  
  25. /* Define to prevent recursive inclusion -------------------------------------*/
  26. #ifndef __OPORA_TIMER_DEFS_H
  27. #define __OPORA_TIMER_DEFS_H
  28.  
  29. /** @addtogroup __CMSIS CMSIS
  30.   * @{
  31.   */
  32.  
  33. /** @addtogroup __OPORA_Peripheral_Units OPORA Peripheral Units
  34.   * @{
  35.   */
  36.  
  37. /** @defgroup Periph_TIMER TIMER
  38.   * @{
  39.   */
  40.  
  41. /** @defgroup Periph_TIMER_Data_Structures Data Structures
  42.   * @{
  43.   */
  44.  
  45. /** @defgroup Periph_TIMER_TypeDef TIMER_TypeDef
  46.   * @{
  47.   */
  48.  
  49. typedef struct {
  50.   __IO uint32_t CNT;
  51.   __IO uint32_t PSG;
  52.   __IO uint32_t ARR;
  53.   __IO uint32_t CNTRL;
  54.   __IO uint32_t CCR1;
  55.   __IO uint32_t CCR2;
  56.   __IO uint32_t CCR3;
  57.   __IO uint32_t CCR4;
  58.   __IO uint32_t CH1_CNTRL;
  59.   __IO uint32_t CH2_CNTRL;
  60.   __IO uint32_t CH3_CNTRL;
  61.   __IO uint32_t CH4_CNTRL;
  62.   __IO uint32_t CH1_CNTRL1;
  63.   __IO uint32_t CH2_CNTRL1;
  64.   __IO uint32_t CH3_CNTRL1;
  65.   __IO uint32_t CH4_CNTRL1;
  66.   __IO uint32_t CH1_DTG;
  67.   __IO uint32_t CH2_DTG;
  68.   __IO uint32_t CH3_DTG;
  69.   __IO uint32_t CH4_DTG;
  70.   __IO uint32_t BRKETR_CNTRL;
  71.   __IO uint32_t STATUS;
  72.   __IO uint32_t IE;
  73.   __IO uint32_t DMA_RE;
  74.   __IO uint32_t CH1_CNTRL2;
  75.   __IO uint32_t CH2_CNTRL2;
  76.   __IO uint32_t CH3_CNTRL2;
  77.   __IO uint32_t CH4_CNTRL2;
  78.   __IO uint32_t CCR11;
  79.   __IO uint32_t CCR21;
  80.   __IO uint32_t CCR31;
  81.   __IO uint32_t CCR41;
  82. } TIMER_TypeDef;
  83.  
  84. /** @} */ /* End of group Periph_TIMER_TypeDef */
  85.  
  86. /** @} */ /* End of group Periph_TIMER_Data_Structures */
  87.  
  88. /** @defgroup Periph_TIMER_Defines Defines
  89.   * @{
  90.   */
  91.  
  92. /** @defgroup Periph_TIMER_TIMER_CNTRL_Bits TIMER_CNTRL
  93.   * @{
  94.   */
  95.  
  96. #define TIMER_CNTRL_CNT_EN_OFFS                 0
  97. #define TIMER_CNTRL_CNT_EN                      ((uint32_t)0x00000001)
  98.  
  99. #define TIMER_CNTRL_ARRB_EN_OFFS                1
  100. #define TIMER_CNTRL_ARRB_EN                     ((uint32_t)0x00000002)
  101.  
  102. #define TIMER_CNTRL_WR_CMPL_OFFS                2
  103. #define TIMER_CNTRL_WR_CMPL                     ((uint32_t)0x00000004)
  104.  
  105. #define TIMER_CNTRL_DIR_OFFS                    3
  106. #define TIMER_CNTRL_DIR                         ((uint32_t)0x00000008)
  107.  
  108. #define TIMER_CNTRL_FDTS_OFFS                   4
  109. #define TIMER_CNTRL_FDTS_MASK                   ((uint32_t)0x00000030)
  110.  
  111. #define TIMER_CNTRL_CNT_MODE_OFFS               6
  112. #define TIMER_CNTRL_CNT_MODE_MASK               ((uint32_t)0x000000C0)
  113.  
  114. #define TIMER_CNTRL_EVENT_SEL_OFFS              8
  115. #define TIMER_CNTRL_EVENT_SEL_MASK              ((uint32_t)0x00000F00)
  116.  
  117.  
  118. /** @} */ /* End of group Periph_TIMER_TIMER_CNTRL_Bits */
  119.  
  120. /** @} */ /* End of group Periph_TIMER_Defines */
  121.  
  122. /** @defgroup Periph_TIMER_Defines Defines
  123.   * @{
  124.   */
  125.  
  126. /** @defgroup Periph_TIMER_TIMER_CH_CNTRL_Bits TIMER_CH_CNTRL
  127.   * @{
  128.   */
  129.  
  130. #define TIMER_CH_CNTRL_CHFLTR_OFFS              0
  131. #define TIMER_CH_CNTRL_CHFLTR_MASK              ((uint32_t)0x0000000F)
  132.  
  133. #define TIMER_CH_CNTRL_CHSEL_OFFS               4
  134. #define TIMER_CH_CNTRL_CHSEL_MASK               ((uint32_t)0x00000030)
  135.  
  136. #define TIMER_CH_CNTRL_CHPSC_OFFS               6
  137. #define TIMER_CH_CNTRL_CHPSC_MASK               ((uint32_t)0x000000C0)
  138.  
  139. #define TIMER_CH_CNTRL_OCCE_OFFS                8
  140. #define TIMER_CH_CNTRL_OCCE                     ((uint32_t)0x00000100)
  141.  
  142. #define TIMER_CH_CNTRL_OCCM_OFFS                9
  143. #define TIMER_CH_CNTRL_OCCM_MASK                ((uint32_t)0x00000E00)
  144.  
  145. #define TIMER_CH_CNTRL_BRKEN_OFFS               12
  146. #define TIMER_CH_CNTRL_BRKEN                    ((uint32_t)0x00001000)
  147.  
  148. #define TIMER_CH_CNTRL_ETREN_OFFS               13
  149. #define TIMER_CH_CNTRL_ETREN                    ((uint32_t)0x00002000)
  150.  
  151. #define TIMER_CH_CNTRL_WR_CMPL_OFFS             14
  152. #define TIMER_CH_CNTRL_WR_CMPL                  ((uint32_t)0x00004000)
  153.  
  154. #define TIMER_CH_CNTRL_CAP_nPWM_OFFS            15
  155. #define TIMER_CH_CNTRL_CAP_nPWM                 ((uint32_t)0x00008000)
  156.  
  157.  
  158. /** @} */ /* End of group Periph_TIMER_TIMER_CH_CNTRL_Bits */
  159.  
  160. /** @} */ /* End of group Periph_TIMER_Defines */
  161.  
  162. /** @defgroup Periph_TIMER_Defines Defines
  163.   * @{
  164.   */
  165.  
  166. /** @defgroup Periph_TIMER_TIMER_CH_CNTRL1_Bits TIMER_CH_CNTRL1
  167.   * @{
  168.   */
  169.  
  170. #define TIMER_CH_CNTRL1_SELOE_OFFS              0
  171. #define TIMER_CH_CNTRL1_SELOE_MASK              ((uint32_t)0x00000003)
  172.  
  173. #define TIMER_CH_CNTRL1_SELO_OFFS               2
  174. #define TIMER_CH_CNTRL1_SELO_MASK               ((uint32_t)0x0000000C)
  175.  
  176. #define TIMER_CH_CNTRL1_INV_OFFS                4
  177. #define TIMER_CH_CNTRL1_INV                     ((uint32_t)0x00000010)
  178.  
  179. #define TIMER_CH_CNTRL1_NSELOE_OFFS             8
  180. #define TIMER_CH_CNTRL1_NSELOE_MASK             ((uint32_t)0x00000300)
  181.  
  182. #define TIMER_CH_CNTRL1_NSELO_OFFS              10
  183. #define TIMER_CH_CNTRL1_NSELO_MASK              ((uint32_t)0x00000C00)
  184.  
  185. #define TIMER_CH_CNTRL1_NINV_OFFS               12
  186. #define TIMER_CH_CNTRL1_NINV                    ((uint32_t)0x00001000)
  187.  
  188.  
  189. /** @} */ /* End of group Periph_TIMER_TIMER_CH_CNTRL1_Bits */
  190.  
  191. /** @} */ /* End of group Periph_TIMER_Defines */
  192.  
  193. /** @defgroup Periph_TIMER_Defines Defines
  194.   * @{
  195.   */
  196.  
  197. /** @defgroup Periph_TIMER_TIMER_CH_DTG_Bits TIMER_CH_DTG
  198.   * @{
  199.   */
  200.  
  201. #define TIMER_CH_DTG_DTGx_OFFS                  0
  202. #define TIMER_CH_DTG_DTGx_MASK                  ((uint32_t)0x0000000F)
  203.  
  204. #define TIMER_CH_DTG_EDTS_OFFS                  4
  205. #define TIMER_CH_DTG_EDTS                       ((uint32_t)0x00000010)
  206.  
  207. #define TIMER_CH_DTG_OFFS                       8
  208. #define TIMER_CH_DTG_MASK                       ((uint32_t)0x0000FF00)
  209.  
  210.  
  211. /** @} */ /* End of group Periph_TIMER_TIMER_CH_DTG_Bits */
  212.  
  213. /** @} */ /* End of group Periph_TIMER_Defines */
  214.  
  215. /** @defgroup Periph_TIMER_Defines Defines
  216.   * @{
  217.   */
  218.  
  219. /** @defgroup Periph_TIMER_TIMER_BRKETR_CNTRL_Bits TIMER_BRKETR_CNTRL
  220.   * @{
  221.   */
  222.  
  223. #define TIMER_BRKETR_CNTRL_BRK_INV_OFFS         0
  224. #define TIMER_BRKETR_CNTRL_BRK_INV              ((uint32_t)0x00000001)
  225.  
  226. #define TIMER_BRKETR_CNTRL_ETR_INV_OFFS         1
  227. #define TIMER_BRKETR_CNTRL_ETR_INV              ((uint32_t)0x00000002)
  228.  
  229. #define TIMER_BRKETR_CNTRL_ETR_PSC_OFFS         2
  230. #define TIMER_BRKETR_CNTRL_ETR_PSC_MASK         ((uint32_t)0x0000000C)
  231.  
  232. #define TIMER_BRKETR_CNTRL_ETR_FILTER_OFFS      4
  233. #define TIMER_BRKETR_CNTRL_ETR_FILTER_MASK      ((uint32_t)0x000000F0)
  234.  
  235.  
  236. /** @} */ /* End of group Periph_TIMER_TIMER_BRKETR_CNTRL_Bits */
  237.  
  238. /** @} */ /* End of group Periph_TIMER_Defines */
  239.  
  240. /** @defgroup Periph_TIMER_Defines Defines
  241.   * @{
  242.   */
  243.  
  244. /** @defgroup Periph_TIMER_TIMER_STATUS_Bits TIMER_STATUS
  245.   * @{
  246.   */
  247.  
  248. #define TIMER_STATUS_CNT_ZERO_EVENT_OFFS        0
  249. #define TIMER_STATUS_CNT_ZERO_EVENT             ((uint32_t)0x00000001)
  250.  
  251. #define TIMER_STATUS_CNT_ARR_EVENT_OFFS         1
  252. #define TIMER_STATUS_CNT_ARR_EVENT              ((uint32_t)0x00000002)
  253.  
  254. #define TIMER_STATUS_ETR_RE_EVENT_OFFS          2
  255. #define TIMER_STATUS_ETR_RE_EVENT               ((uint32_t)0x00000004)
  256.  
  257. #define TIMER_STATUS_ETR_FE_EVENT_OFFS          3
  258. #define TIMER_STATUS_ETR_FE_EVENT               ((uint32_t)0x00000008)
  259.  
  260. #define TIMER_STATUS_BRK_EVENT_OFFS             4
  261. #define TIMER_STATUS_BRK_EVENT                  ((uint32_t)0x00000010)
  262.  
  263. #define TIMER_STATUS_CCR_CAP_EVENT_OFFS         5
  264. #define TIMER_STATUS_CCR_CAP_EVENT_MASK         ((uint32_t)0x000001E0)
  265.  
  266. #define TIMER_STATUS_CCR_REF_EVENT_OFFS         9
  267. #define TIMER_STATUS_CCR_REF_EVENT_MASK         ((uint32_t)0x00001E00)
  268.  
  269. #define TIMER_STATUS_CCR1_CAP_EVENT_OFFS        13
  270. #define TIMER_STATUS_CCR1_CAP_EVENT_MASK        ((uint32_t)0x0001E000)
  271.  
  272.  
  273. /** @} */ /* End of group Periph_TIMER_TIMER_STATUS_Bits */
  274.  
  275. /** @} */ /* End of group Periph_TIMER_Defines */
  276.  
  277. /** @defgroup Periph_TIMER_Defines Defines
  278.   * @{
  279.   */
  280.  
  281. /** @defgroup Periph_TIMER_TIMER_IE_Bits TIMER_IE
  282.   * @{
  283.   */
  284.  
  285. #define TIMER_IE_CNT_ZERO_EVENT_IE_OFFS         0
  286. #define TIMER_IE_CNT_ZERO_EVENT_IE              ((uint32_t)0x00000001)
  287.  
  288. #define TIMER_IE_CNT_ARR_EVENT_IE_OFFS          1
  289. #define TIMER_IE_CNT_ARR_EVENT_IE               ((uint32_t)0x00000002)
  290.  
  291. #define TIMER_IE_ETR_RE_EVENT_IE_OFFS           2
  292. #define TIMER_IE_ETR_RE_EVENT_IE                ((uint32_t)0x00000004)
  293.  
  294. #define TIMER_IE_ETR_FE_EVENT_IE_OFFS           3
  295. #define TIMER_IE_ETR_FE_EVENT_IE                ((uint32_t)0x00000008)
  296.  
  297. #define TIMER_IE_BRK_EVENT_IE_OFFS              4
  298. #define TIMER_IE_BRK_EVENT_IE                   ((uint32_t)0x00000010)
  299.  
  300. #define TIMER_IE_CCR_CAP_EVENT_IE_OFFS          5
  301. #define TIMER_IE_CCR_CAP_EVENT_IE_MASK          ((uint32_t)0x000001E0)
  302.  
  303. #define TIMER_IE_CCR_REF_EVENT_IE_OFFS          9
  304. #define TIMER_IE_CCR_REF_EVENT_IE_MASK          ((uint32_t)0x00001E00)
  305.  
  306.  
  307. /** @} */ /* End of group Periph_TIMER_TIMER_IE_Bits */
  308.  
  309. /** @} */ /* End of group Periph_TIMER_Defines */
  310.  
  311. /** @defgroup Periph_TIMER_Defines Defines
  312.   * @{
  313.   */
  314.  
  315. /** @defgroup Periph_TIMER_TIMER_DMA_RE_Bits TIMER_DMA_RE
  316.   * @{
  317.   */
  318.  
  319. #define TIMER_DMA_RE_CNT_ZERO_EVENT_RE_OFFS     0
  320. #define TIMER_DMA_RE_CNT_ZERO_EVENT_RE          ((uint32_t)0x00000001)
  321.  
  322. #define TIMER_DMA_RE_CNT_ARR_EVENT_RE_OFFS      1
  323. #define TIMER_DMA_RE_CNT_ARR_EVENT_RE           ((uint32_t)0x00000002)
  324.  
  325. #define TIMER_DMA_RE_ETR_RE_EVENT_RE_OFFS       2
  326. #define TIMER_DMA_RE_ETR_RE_EVENT_RE            ((uint32_t)0x00000004)
  327.  
  328. #define TIMER_DMA_RE_ETR_FE_EVENT_RE_OFFS       3
  329. #define TIMER_DMA_RE_ETR_FE_EVENT_RE            ((uint32_t)0x00000008)
  330.  
  331. #define TIMER_DMA_RE_BRK_EVENT_RE_OFFS          4
  332. #define TIMER_DMA_RE_BRK_EVENT_RE               ((uint32_t)0x00000010)
  333.  
  334. #define TIMER_DMA_RE_CCR_CAP_EVENT_RE_OFFS      5
  335. #define TIMER_DMA_RE_CCR_CAP_EVENT_RE_MASK      ((uint32_t)0x000001E0)
  336.  
  337. #define TIMER_DMA_RE_CCR_REF_EVENT_RE_OFFS      9
  338. #define TIMER_DMA_RE_CCR_REF_EVENT_RE_MASK      ((uint32_t)0x00001E00)
  339.  
  340.  
  341. /** @} */ /* End of group Periph_TIMER_TIMER_DMA_RE_Bits */
  342.  
  343. /** @} */ /* End of group Periph_TIMER_Defines */
  344.  
  345. /** @defgroup Periph_TIMER_Defines Defines
  346.   * @{
  347.   */
  348.  
  349. /** @defgroup Periph_TIMER_TIMER_CH_CNTRL2_Bits TIMER_CH_CNTRL2
  350.   * @{
  351.   */
  352.  
  353. #define TIMER_CH_CNTRL2_CHSEL1_OFFS             0
  354. #define TIMER_CH_CNTRL2_CHSEL1_MASK             ((uint32_t)0x00000003)
  355.  
  356. #define TIMER_CH_CNTRL2_CCR1_EN_OFFS            2
  357. #define TIMER_CH_CNTRL2_CCR1_EN                 ((uint32_t)0x00000004)
  358.  
  359. #define TIMER_CH_CNTRL2_CCRRLD_OFFS             3
  360. #define TIMER_CH_CNTRL2_CCRRLD                  ((uint32_t)0x00000008)
  361.  
  362.  
  363. /** @} */ /* End of group Periph_TIMER_TIMER_CH_CNTRL2_Bits */
  364.  
  365. /** @} */ /* End of group Periph_TIMER_Defines */
  366.  
  367. /** @} */ /* End of group Periph_TIMER */
  368.  
  369. /** @} */ /* End of group __OPORA_Peripheral_Units */
  370.  
  371. /** @} */ /* End of group __CMSIS */
  372.  
  373. #endif /* __OPORA_TIMER_DEFS_H */
  374.  
  375. /******************* (C) COPYRIGHT 2010 Phyton *********************************
  376. *
  377. * END OF FILE opora_timer_defs.h */
  378.